Mitul Tandon

tandonmitul27@iitb.ac.in / tandonmitul27@gmail.com

I am a 4th year Dual Degree student in the Electrical Engineering Department at Indian Institute of Technology Bombay (IITB).
My area of interest lies in computer architecture, especially Processing-in-Memory and LLM Serving.

News

Sep. 2025 – Excited to start my semester exchange at the School of Electrical Engineering, KAIST, South Korea!

Aug. 2025 – Happy to share that our paper LiC has been accepted at VLSI-SoC 2025.

Jun. 2025 – Glad to receive the Global Korea Scholarship (GKS) to support my semester exchange at KAIST.

Publications

Research Experience

Improving Memory Subsystem Efficiency for Graph Analytics

Prof. Virendra Singh

Developed and modeled a hardware-based, data-aware prefetching mechanism to optimize on-chip cache utilization for graph analytics, achieving up to 78% speedup over baseline and 16% over state-of-the-art DROPLET prefetcher accross applications on the GAP Benchmark Suite using Sniper simulator.

Dec 2024 - May 2025
IIT Bombay
Research Details
  • Analyzed hardware-based prefetching mechanisms such as DROPLET, along with cache management techniques like GRACE to optimize on-chip cache utilization and accelerate graph processing.
  • Proposed and modeled a hardware-based, data-aware prefetching mechanism designed for graph analytics applications.
  • Achieved up to 78% performance improvement over the baseline and 16% improvement over the state-of-the-art hardware prefetcher DROPLET across applications in the GAP Benchmark Suite, using the Sniper simulator.

Low Cost Cache Replacement Policy

Prof. Virendra Singh

Designed and evaluated a lightweight cache replacement policy for all cache levels, achieving up to 28× storage reduction compared to state-of-the-art policies (NMRU, PLRU, SRRIP, SHiP, Hawkeye) with negligible performance loss, validated through ChampSim simulator.

Jan 2025 - Mar 2025
IIT Bombay
Research Details
  • Proposed a lightweight cache replacement policy for the entire cache hierarchy (all levels), focusing on reduced area, lower power consumption and a simplified decision-making algorithm.
  • Implemented pseudo-LRU (tree-based) and NRU (1-bit RRPV version of SRRIP) replacement policies and performed a comparative analysis of the proposed policy against various other replacement policies using the ChampSim simulator
  • Achieved significant storage reduction, lowering requirements by factors of 4x, 3.75x, 16x, 14x and 28x compared to NMRU, pseudo-LRU, LRU/SRRIP/DRRIP, SHiP and Hawkeye respectively with negligible performance loss.

Set Associative 3D DRAM Caches

Prof. Biswabandan Panda

Conducted an in-depth study of 3D DRAM technologies (HBM, HMC) and stacking architecures, then implemented and evaluated a 64 MB set-associative HBM cache tag array using ChampSim, achieving 8.5% improvement over direct-mapped HBM and 24.27% speedup over baseline.

Aug 2024 - Nov 2024
IIT Bombay
Research Details
  • Conducted a literature review on 3D DRAM technologies, including High Bandwidth Memory and Hybrid Memory Cube to understand their architecture, core functionalities, and potential for high-bandwidth applications.
  • Performed an in-depth analysis of SILO, which discusses the use of a private die-stacked DRAM cache similar to HMC.
  • Developed a 64 MB HMC tag array for an HBM cache using the ChampSim simulator, enabling set associativity in HBM.
  • Achieved an 8.5% improvement over the directly mapped HBM cache and a 24.27% speedup compared to the baseline.

Processing Data Where It Makes Sense

Prof. Virendra Singh

Conducted an extensive literature review on processing-in-memory (PIM) and explored PIM simulators like ZSim+Ramulator to understand their capabilities for modeling and evaluating PIM systems.

Jun 2024 - JUl 2024
IIT Bombay
Research Details
  • Conducted an extensive literature review on processing-in-memory, and the simulators used to simulate PIM systems.
  • Analyzed the Ramulator paper and reproduced its results using the corresponding simulator (Ramulator), involving a comparison of IPC metrics across various DRAM standards with 22 benchmarks from the SPEC2006 suite.
  • Used ZSim+Ramulator to simulate multiple benchmarks from the DAMOV suite, comparing IPC and cycle counts across host, PIM, and host with prefetcher systems, with PIM systems leveraging computations in the logic layer of an HMC.

Projects

Pipelined RISC Processor

EE 309: Microprocessors | Prof. Virendra Singh

Designed and implemented a 16-bit 6-stage pipelined processor supporting predicated execution, multiple load/store operations, branch prediction, and hazard mitigation, programmed in VHDL.

Mar 2024 - May 2024
IIT Bombay
Project Details
  • Designed IITB-RISC, a 16-bit 6-stage pipelined processor supporting predicated execution, multiple load/store operations, and branch prediction.
  • Implemented hazard mitigation with stalling, flushing, data forwarding, and a history-bit-based branch predictor, which reduced stalls and improved the overall IPC.
  • Programmed the complete datapath using a mix of behavioral and structural VHDL.
  • Tested the system rigorously with an extensive custom instruction set in ModelSim to ensure correctness.

Multicycle Architecture Processor

EE 224: Digital Systems | Prof. Virendra Singh

Designed and implemented a 16-bit processor supporting R/I/J instruction types and a 14-instruction Turing-complete ISA, programmed in VHDL and tested on ALTERA MAX-10 FPGA.

Nov 2023 - Jan 2024
IIT Bombay
Project Details
  • Modeled IITB-CPU, a 16-bit processor with 8 registers, supporting R/I/J instructions and a 14-instruction Turing-complete ISA.
  • Programmed core components including ALU, Register File, Memory Unit, and controller, using structural VHDL for optimized testing on Xen-10 FPGA.
  • Created comprehensive digital documentation with FSMs, flowcharts, and component designs to validate all instructions and system functionalities.

Logic Analyzer for PicoIRIS

Summer Project | Wadhwani Electronics Lab | Prof. Siddharth Tallur

Integrated logic analyzer functionality into PicoIRIS for digital signal analysis, programmed PIC32 for Bluetooth UART communication with 500 kHz sampling, and built a Qt–Python GUI for real-time data visualization and UART debugging.

Jun 2024 - Jul 2024
IIT Bombay
Project Details
  • Upgraded the in-house PicoIRIS PCB by adding logic analyzer capabilities for academic digital signal analysis.
  • Programmed PIC32 for Bluetooth UART communication, enabling data sampling up to 500 kHz for debugging UART, I2C, and SPI signals.
  • Developed a Qt-based GUI integrated with Python backend for interactive data visualization and UART analysis.

Colorization of B/W Images using DNN

WiDS 2023 | Analytics Club

Implemented and iteratively refined deep learning models for automatic colorization of black-and-white images, leveraging Transfer Learning with Inception-ResNet-v2 to improve object recognition and color accuracy.

Dec 2023 - Jan 2024
IIT Bombay
Project Details
  • Preprocessed the MNIST dataset using Python libraries and trained a CNN with Batch Normalization in PyTorch for efficient digit classification.
  • Evaluated and optimized model performance using accuracy metrics, precision, recall, F1-score, and confusion matrices.
  • Implemented Alpha, Beta, and Final colorization models, integrating Inception-ResNet-v2 via Transfer Learning to enhance object understanding and coloring accuracy.

Teaching Experience

Digital Systems (EE 224)

Teaching Assistant

  • Sole undergraduate TA for a class of 95+ students, managing course logistics and coordinating with graduate TAs.

  • Conducted weekly test invigilation, graded assessments, developed quiz solutions and evaluation rubrics, and held regular doubt-solving sessions for student mentorship.

Mar 2024 - May 2024
IIT Bombay

Academics

Department of Electrical Engineering

  • EEXYZ – Introduction to Optimization*†

  • EEXYZ – Electronics Design Lab <Advanced Digital System Design>*†

  • EE739 – Processor Design

  • EE338 – Digital Signal Processing

  • EE344 – Electronic Design Lab

  • EE350 – Technical Communication

  • EE691 – R & D Project

  • EE789 – Algorithmic Design of Digital Systems

  • EE236 – Electronic Devices Lab

  • EE301 – Electromagnetic Waves

  • EE324 – Control Systems Lab

  • EE340 – Communications Lab

  • EE341 – Communication Systems - I

  • EE353 – Introduction to Data Science and Machine Learning

  • EE207 – Electronic Devices & Circuits

  • EE230 – Analog Lab

  • EE238 – Power Engineering - II

  • EE240 – Power Engineering Lab

  • EE302 – Control Systems

  • EE309 – Microprocessors

  • EE337 – Microprocessors Laboratory

  • EE114 – Power Engineering - I

  • EE204 – Analog Circuits

  • EE214 – Digital Circuits Lab

  • EE224 – Digital Systems

  • EE229 – Signal Processing - I

  • EE325 – Probability and Random Processes

Department of Computer Science & Engineering

  • CSXYZ – Introduction to Artificial Intelligence*†

  • CS490 – R & D Project

  • CS207 – Discrete Structures

  • CS101 – Computer Programming and Utilization


Department of Biosciences and Bioengineering


Centre for Machine Intelligence and Data Science

  • DS203 – Programming for Data Science


Department of Mathematics

  • MA108 – Differential Equations

  • MA106 – Linear Algebra

  • MA111 – Calculus II

  • MA109 – Calculus I


Department of Physics

  • PH112 – Introduction to Quantum Physics

  • PH111 – Introduction to Classical Physics

  • PH117 – Physics Lab

*Ongoing, to be completed by Dec'25.

†Courses taken at KAIST.

Photography

I've always found photography to be one of the most powerful ways we can express ourselves. It's more than just snapping a picture. It's a way to pause a fleeting moment, tell a story, and share a unique perspective. I hope you enjoy seeing the world through my eyes.

Caged Minds

This series captures the quiet struggles of student life — the weight of deadlines, the feeling of being caged by expectations, and the small temptations of joy that lie just outside reach. As the images progress, so does the light, mirroring the shift in mood from despair to a search for relief.

Sep 2025
Daejeon, South Korea
Caged Minds photo 1

1. The Breaking Point

Caged Minds photo 2

2. Trapped

Caged Minds photo 3

3. The Temptation

Caged Minds photo 4

4. Reaching Out

Caged Minds photo 5

5. Breaking Free

Clouds are heavier than we think

Coming Soon...

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Daejeon, South Korea

Chaos

Coming Soon...

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Daejeon, South Korea